Title :
IEE Colloquium on `High Level Modelling and Design for ASICs´ (Digest No.120)
Abstract :
The following topics were dealt with: gate array design; digital circuits simulation on transputers; design automation based upon distributed self-timed architecture; high level behavioural modelling and simulation of mixed analog-digital ASICs; using knowledge based systems with CAD; System 1076, a graphical VHDL design environment; logic synthesis from a hardware description language; behavioural and structural synthesis systems; and formal system design
Keywords :
application specific integrated circuits; circuit layout CAD; logic CAD; CAD; System 1076; behavioural synthesis system; design automation; digital circuits simulation; distributed self-timed architecture; formal system design; gate array design; graphical VHDL design environment; hardware description language; high level behavioural modelling; knowledge based systems; logic synthesis; mixed analog-digital ASICs; simulation; structural synthesis systems; transputers;
Conference_Titel :
High Level Modelling and Design for ASICs, IEE Colloquium on
Conference_Location :
London
