Design automation based upon a distributed self-timed architecture

This paper describes a design automation tool for digital systems, ZP, which incorporates both system level correctness checking of control and data flow and automatic translation to a hardware or software target. It differs from typical `silicon compiler´ tools both in the provision of analytical routines which detect characteristics such as correct termination and freedom from indeterminacy and deadlock in concurrent systems, and in that the output data is not tied into a particular language or technology, allowing access to a range of implementations. The current version of ZP contains synthesis routines which generate hardware components comprising the controller and data paths of a design in a form suitable for input to existing VLSI layout packages