CAD for dual-Vth CMOS circuits

Leakage power has become one of the major obstacles to Moore´s law. Unless, leakage power is lowered by orders of magnitude, we cannot enjoy the progress that technology scaling offers. Dual-V_th has emerged as an increasingly important technology that achieves very low standby leakage power, while maintaining high-performance. This paper provides a comprehensive overview of design issues related to digital integrated circuits with embedded dual-V_th. It is shown that the methodology to optimally design such dual-V_th circuits must involve: (1) accurate modeling of the gate delays in the design, and (2) efficient estimation of the leakage current in every gate. The power minimization problem is then defined, taking all possible design criteria into account. The choice of the value of the threshold voltages is finally addressed.