Abstract :
VHDL is a hardware description language `intended for use in all phases of the creation of electronic systems´ which was initially sponsored by the America DoD and has since been adopted as standard number 1076-1987 by the IEEE. The quote above is taken from the preface to the IEEE specification document, published in 1987. Commercial acceptance of VHDL is growing rapidly, as shown by the endorsement of VHDL by the influential component purchasing group, STACK. This paper provides a very brief introduction to the VHDL language, followed by the description of an innovative tool for simulation using VHDL and other hardware modelling methods
