Title :
A primary planner for high-level architectural synthesis
Author :
Beikzadeh, M.R. ; Mack, R.J.
Author_Institution :
Dept. of Electron. Syst. Eng., Essex Univ., Colchester, UK
Abstract :
The authors present an integrated internal representation, a primary plan, as a basis for the automatic synthesis of a register transfer architecture from a behavioural description. The structure of a prototype synthesis system is presented, and the generation of the primary plan is discussed in detail. The system operates by adopting a hierarchical approach and transforming the initial abstract representation of the plan to a hardware structure which meets specified speed and hardware constraints. An example is given showing how different user constraints produce alternative architectures
Keywords :
circuit layout CAD; logic CAD; scheduling; CAD; behavioural description; hardware structure; high-level architectural synthesis; primary planner; prototype synthesis system; register transfer architecture; Automatic control; Chip scale packaging; Clocks; Design automation; Design engineering; Hardware; High level synthesis; Prototypes; Registers; Systems engineering and theory;
Conference_Titel :
Circuits and Systems, 1990., Proceedings of the 33rd Midwest Symposium on
Conference_Location :
Calgary, Alta.
Print_ISBN :
0-7803-0081-5
DOI :
10.1109/MWSCAS.1990.140891