DocumentCode :
2825189
Title :
Tutorial - reliability enhancement for high-performance circuits in deep sub-micron era
Author :
Chrzanowska-Jeske, Malgorzata
Author_Institution :
Electr. & Comput. Eng., Portland State Univ., OR, USA
Volume :
3
fYear :
2003
fDate :
27-30 Dec. 2003
Firstpage :
1474
Abstract :
Scaling of the device dimensions has introduced various "analog" effects on-chip that are causing signal integrity and delay problems. Moreover, technology scaling is moving high-performance ICs toward higher power dissipation. Thermal conditions of the chip directly influence reliability as many of the basic mechanisms responsible for the life-time of a chip are strong functions of temperature. This tutorial discusses the fundamental mechanisms associated with integrated circuit interconnect reliability and will discuss approaches for the interconnect reliability enhancement through layout changes.
Keywords :
integrated circuit interconnections; integrated circuit reliability; analog effects; deep sub-micron era; device scaling; high performance circuits; integrated circuit interconnect; reliability enhancement; signal delay; signal integrity;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2003 IEEE 46th Midwest Symposium on
ISSN :
1548-3746
Print_ISBN :
0-7803-8294-3
Type :
conf
DOI :
10.1109/MWSCAS.2003.1562574
Filename :
1562574
Link To Document :
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