Implementation of the εpsilon dataflow processor

Based on an operation-level, static dataflow model of computation, the processor uses a directly addressed matching store rather than a traditional associative matching store. The design is implemented with off-the-shelf ICs on a single circuit board. Sustained performance comparable to that of commercial minisupercomputers is demonstrated. Two variations of the processor architecture are constructed, with the second building extensively on the experience gained from the first. The second prototype is studied in great detail, and the resulting insights lead to the development of a new architecture, εpsilon-2. The architectures and specific implementations involved in this progression are described. The knowledge gained in the physical construction and the performance assessment of each are presented along with the resulting architectural modifications