Title :
Combinational Divider in FPGA
Author :
Kolouch, Jaromir
Author_Institution :
Brno Univ. of Technol., Brno
Abstract :
The possibility of synthesis of combinational divider for unsigned integer numbers in FPGA devices is considered with respect to recent technology development. Three VHDL models are discussed, and corresponding synthesis and implementation results - resource consumption and propagation delay, together with the bit width limitation, are compared.
Keywords :
delays; digital arithmetic; dividing circuits; field programmable gate arrays; hardware description languages; FPGA; VHDL models; arithmetic functions; bit width limitation; combinational divider synthesis; combinational logic; propagation delay; resource consumption; unsigned integer numbers; Algorithm design and analysis; Arithmetic; Circuit synthesis; Combinational circuits; Field programmable gate arrays; Manufacturing; Programmable logic arrays; Programmable logic devices; Propagation delay; Writing; Arithmetic functions; FPGA; combinational logic; integer division; propagation delay; synthesis;
Conference_Titel :
Radioelektronika, 2007. 17th International Conference
Conference_Location :
Brno
Print_ISBN :
1-4244-0821-0
Electronic_ISBN :
1-4244-0822-9
DOI :
10.1109/RADIOELEK.2007.371427
