An iterated FIR filter using radix-4 serial arithmetic for gallium arsenide technology

Author

Chew, Kay C. ; North, Richard C. ; Ku, Walter H.

Author_Institution

Dept. of ECE, California Univ., San Diego, La Jolla, CA, USA

fYear

1991

fDate

11-14 Jun 1991

Firstpage

500

Abstract

The architecture of an iterated FIR (finite impulse response) filter using radix-4 serial/parallel multipliers and radix-4 serial adder/subtractors is presented. The architecture is targeted for ultra-high-speed technologies, in particular GaAs MESFET and HEMT (high electron mobility transistor) technologies. A serial arithmetic approach is proposed for this high-speed but relatively low integration level technology in order to reduce the size of the integrated circuit. The authors give a description of the iterated FIR filter structure and discuss two possible approaches to implementing the FIR algorithm in GaAs

Keywords

III-V semiconductors; VLSI; digital filters; field effect integrated circuits; gallium arsenide; GaAs; HEMT technology; MESFET technology; filter structure; iterated FIR filter; low integration level technology; radix-4 serial arithmetic; semiconductors; serial arithmetic approach; ultra-high-speed technologies; Arithmetic; CMOS logic circuits; CMOS technology; Convolution; Finite impulse response filter; Gallium arsenide; High speed integrated circuits; Integrated circuit noise; Integrated circuit technology; Postal services;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1991., IEEE International Sympoisum on

Print_ISBN

0-7803-0050-5

Type

conf

DOI

10.1109/ISCAS.1991.176382

Filename

176382