High performance III–V FETs for low power CMOS applications

III-V compound semiconductor based quantum well field effect transistors are in general viewed as a promising transistor candidate for future high-speed low-power logic applications due to their excellent drive current performance at low voltage. In this presentation, I will review recent device developments of n-channel InGaAs transistors. To start, well-studied Schottky gate device architecture is adopted to demonstrate integration on Si substrate [1] as well as to establish performance advantages over state-of-the-art Si NMOS at V_CC=0.5V [2]. To enable further L_G scaling, high quality high-K dielectric is integrated [3] and non-planar Tri-gate architecture is implemented [4]. I will conclude by discussing InSb based p-channel device results [5], as well as InGaAs based tunnel FETs [6].