Title :
III–V 4D transistors
Author :
Gu, J.J. ; Wang, X.W. ; Shao, J. ; Neal, A.T. ; Manfra, M.J. ; Gordon, R.G. ; Ye, P.D.
Author_Institution :
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Abstract :
We fabricated for the first time vertically and laterally integrated III-V 4D transistors. III-V gate-all-around (GAA) nanowire MOSFETs with 3×4 arrays show high drive current of 1.35mA/μm and high transconductance of 0.85mS/μm. The vertical stacking of the III-V nanowires have provided an elegant solution to the drivability bottleneck of nanowire devices and is promising for future low-power logic and RF application.
Keywords :
III-V semiconductors; MOSFET; gallium arsenide; indium compounds; nanowires; wide band gap semiconductors; III-V 4D transistor; III-V gate-all-around nanowire MOSFET; InGaAs; RF application; drivability bottleneck; laterally integrated III-V 4D transistor; low-power logic application; nanowire device; transconductance; vertical stacking; vertically integrated III-V 4D transistor; Fabrication; Indium gallium arsenide; Indium phosphide; Logic gates; MOSFETs; Nanobioscience; Nanoscale devices;
Conference_Titel :
Device Research Conference (DRC), 2012 70th Annual
Conference_Location :
University Park, TX
Print_ISBN :
978-1-4673-1163-2
DOI :
10.1109/DRC.2012.6256964
