Efficient selective compaction and un-compaction of inconsequential logical design units in the schematic representation of a design

Design for Test (DFT) introduces certain elements such as buffers, inverter-pairs etc, though inconsequential, are integral part of a digital design. However, while debugging a circuit schematically, they waste precious real estate when a designer is mostly interested in the logical design elements. At the same time, it is important that these inconsequential elements are not discarded altogether as they could play an important role in the DFT debugging process such as buffer at pin output that fans out to multiple gates preserving the pin´s hierarchical information when a design is flattened into primitives. This paper presents a novel approach that allows a designer to efficiently compact/un-compact inconsequential design components both completely/selectively in the design schematic, thus aiding the structural debugging process.