DocumentCode
283197
Title
An overview of ASIC design methodology
Author
Morling, R.C.S.
Author_Institution
Centre for Microelectron. Syst. Applications, Polytech. of Central London, UK
fYear
1988
fDate
32252
Firstpage
42370
Lastpage
110
Abstract
The approach now most often used with low-cost prototyping of gate arrays and custom designs is that of the Multi-Chip Wafer (MCW). Here different designs are mixed on the same wafer using electron beam lithography. A further refinement of this technique is to use an electron beam to directly write the pattern onto the wafer surface. This, in theory at least, provides the fastest prototype turnaround. It is often erroneously thought that production quantities must be in the thousands before custom chips can be considered. This is certainly not the case especially with gate arrays where a production requirement of 50 can be economic. In estimating the relative costings of a custom chip versus a number of catalogue part ICs, the saving in board space, number of cards required, number of PCB layers required, etc. should be taken into consideration. Even if the custom chip costs more than the catalogue parts it often will be cheaper to use the ASIC because of these other savings
Keywords
cellular arrays; digital integrated circuits; electron beam lithography; ASIC; ASIC design methodology; Multi-Chip Wafer; PCB layers; board space; costings; custom designs; electron beam lithography; gate arrays; low-cost prototyping; production requirement; wafer surface;
fLanguage
English
Publisher
iet
Conference_Titel
Managing ASIC Design Projects, IEE Colloquium on
Conference_Location
London
Type
conf
Filename
209096
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