IIR double-sampled switched-capacitor building blocks for high-frequency decimators

The possibility of implementing the double-sampling (DS) technique in IIR first- and second-order switched-capacitor (SC) decimator building blocks is considered. The circuits which result follow the same design procedure of standard IIR decimators, and only a different switched-capacitor implementation results with a re-organized clock phasing. The main advantage is that the time allowed for the op amps to settle can be equal to the output sampling period rather than one half of it. Using the proposed double-sampled decimator allows one to design high-frequency SC filtering systems (anti-aliasing decimator filter and core double-sampled filter) where the speed requirements in each block are similar so as to optimize the overall circuit design