Extended data retention process technology for highly reliable flash EEPROMs of 10/sup 6/ to 10/sup 7/ W/E cycles

Using 16 Mbit flash memories, we clarified the relationship between data retention and Si surface micro-defects just before the tunnel oxidation process. After 10/sup 5/ to 10/sup 6/ write/erase cycles, a small number of singular cells appear to have an anomalously large charge loss rate, when the Si surface defect density due to process damage exceeds 1.2/spl times/10/sup 20//cm/sup 3/. This anomalous charge loss phenomenon strongly depends on the electric field in the tunnel oxide, which is caused by the stored charge in the floating gate. Thus, an accelerated data retention test can be performed by means of the electric field in the tunnel oxide, by controlling the programmed V/sub t/ to be more than 2.4 V just before the retention test (here, neutral V/sub t/ is adjusted to 0 V). By using an accelerated test, it is clarified that controlling the number of surface micro-defects is important in order to obtain extended data retention characteristics. By reducing the surface micro-defects to less than 1.2/spl times/10/sup 20//cm/sup 3/, the data retention reliability after 10/sup 6/ to 10/sup 7/ write/erase cycles can be guaranteed for conventional 2-level flash memories, where programmed V/sub t/ is less than 2.4 V.