DocumentCode
2833864
Title
An algorithm for three-layer channel routing with via minimization
Author
Song, Xuejun ; Li, Wangchao ; Liu, Meilun
Author_Institution
Dept. of Electr. Eng. & Autom., Tianjin Univ., China
fYear
1991
fDate
11-14 Jun 1991
Firstpage
1944
Abstract
An algorithm for three-layer channel routing with via minimization is presented. It aims at minimizing both the number of vias and the number of tracks. The algorithm has been coded in Pascal and implemented on an XT/286 computer. Experimental results show that, compared with HVH routing, the numbers of vias are decreased by about 40-50% and, for some examples, the numbers of tracks are also less than those of known results. Besides, the routability is 100% regardless of whether there exists a cycle vertical constraint or not
Keywords
circuit layout CAD; minimisation; XT/286 computer; three-layer channel routing; via minimization; Automation; Filling; Minimization methods; Routing;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1991., IEEE International Sympoisum on
Print_ISBN
0-7803-0050-5
Type
conf
DOI
10.1109/ISCAS.1991.176789
Filename
176789
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