• DocumentCode
    2834166
  • Title

    Fault diagnosis with short circuit for linear analog networks

  • Author

    Sakaguchi, Kazuhiro ; Kaneko, Mineo

  • Author_Institution
    Dept. of Electr. & Electron. Eng., Tokyo Inst. of Technol., Japan
  • fYear
    1991
  • fDate
    11-14 Jun 1991
  • Firstpage
    2068
  • Abstract
    A novel method to prepare the fault dictionary for the short circuit faults in linear analog networks is proposed. In this method, the whole dictionary can be made with computational complexity O(n3), where n denotes the number of nodes in the network. The authors discuss the volume of the dictionary, and an alternative fault diagnosis algorithm is presented, in which memories for the dictionary can be reduced to 2/m2 times compared with the conventional algorithm, where m is the number of accessible nodes
  • Keywords
    analogue circuits; automatic test equipment; circuit analysis computing; fault location; computational complexity; fault diagnosis algorithm; fault dictionary; linear analog networks; number of nodes; short circuit; short circuit faults; Admittance; Artificial intelligence; Circuit faults; Computational complexity; Dictionaries; Equations; Fault diagnosis; Matrix decomposition; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1991., IEEE International Sympoisum on
  • Print_ISBN
    0-7803-0050-5
  • Type

    conf

  • DOI
    10.1109/ISCAS.1991.176811
  • Filename
    176811
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2834166