High speed CMOS chip to chip communication circuit

Author

Svensson, Christer ; Yuan, Jiren

Author_Institution

LSI Design Center, IFM, Linkoping Univ., Sweden

fYear

1991

fDate

11-14 Jun 1991

Firstpage

2228

Abstract

Communication circuits between chips through transmission lines are demonstrated. In standard packages, a single-output 75-Ω line driver in a 2-μm CMOS process reaches a data rate of 700 Mb/s, and a differential-output 50-Ω line driver plus a receiver in a 1.2-μm CMOS process works up to a data rate of 1 Gb/s. By using leadless chip carriers, the 75-Ω line driver in a 1.2-μm CMOS process gives a maximum data rate of 1.3 Gb/s. These are measured results. The differential driver and receiver should be able to work at a data rate of 1.25 Gb/s with a leadless chip carrier. The impact of packaging on high speed chip to chip communication is discussed

Keywords

CMOS integrated circuits; buffer circuits; digital integrated circuits; driver circuits; packaging; 1.2 micron; 2 micron; 50 ohm; 700 to 1300 Mbit/s; 75 ohm; CMOS chip to chip communication circuit; communication between chips; data rate; differential driver; differential-output; high speed chip to chip communication; impact of packaging; leadless chip carriers; line driver; measured results; standard packages; transmission lines; CMOS process; CMOS technology; Distributed parameter circuits; Driver circuits; Energy consumption; Frequency; Large scale integration; Packaging; Power transmission lines; Semiconductor device measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1991., IEEE International Sympoisum on

Print_ISBN

0-7803-0050-5

Type

conf

DOI

10.1109/ISCAS.1991.176820

Filename

176820