Analysis of VLSI interconnects with nonlinear terminations

Author

Tang, Tak K. ; Nakhla, Michel ; Griffith, Rean

Author_Institution

Carleton Univ., Ottawa, Ont., Canada

fYear

1991

fDate

11-14 Jun 1991

Firstpage

2339

Abstract

A method is described for delay estimation of VLSI interconnects with nonlinear terminations. The method is based on piecewise decomposition and asymptotic waveform evaluation (AWE) techniques which offer two to three orders of magnitude speedup when compared to conventional circuit simulators. The analysis method involves four steps. 1. The network equations are formulated using the modified-nodal admittance matrix. 2. Using the piecewise decomposition technique, the nonlinear terminations are replaced by time-dependent sources. 3. The transient response of the resulting linear network is obtained using the AWE technique. 4. The parameters defining the time-dependent sources are evaluated using an iterative technique. The analysis algorithm can be extended to interconnects which contain distributed elements

Keywords

VLSI; delays; metallisation; nonlinear network analysis; transmission line theory; AWE technique; VLSI interconnects; asymptotic waveform evaluation; delay estimation; four step method; iterative technique; modified-nodal admittance matrix; nonlinear terminations; piecewise decomposition; speedup; time-dependent sources; transient response; Admittance; Algorithm design and analysis; Circuit simulation; Delay estimation; Integrated circuit interconnections; Iterative algorithms; Matrix decomposition; Nonlinear equations; Transient response; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1991., IEEE International Sympoisum on

Print_ISBN

0-7803-0050-5

Type

conf

DOI

10.1109/ISCAS.1991.176847

Filename

176847