A test methodology for VLSI circuits

Presents a brief overview of work on testing currently being carried out under the Alvey CAD042 research initiative at Oxford University. A test methodology is being evolved to exploit the hierarchical properties of circuit designs when generating test patterns. The goal of the research is to define a method by which pre-computed test vectors for modules may be combined to form a complete test set for the circuit as a whole. The work is in an early stage of development but initial results, with circuit examples provided by industrial partners in the CAD042 group, have been promising