• DocumentCode
    2836637
  • Title

    Design and analysis of a fault tolerant multiprocessor system with failsafe and failsafe-redundant interfacing schemes

  • Author

    Chande, P.K. ; Ramani, A.K. ; Sharma, P.C.

  • Author_Institution
    Dept. of Electron. & Comput. Eng., Shri G.S. Inst. of Technol. & Sci., Indore, India
  • fYear
    1989
  • fDate
    22-24 Nov 1989
  • Firstpage
    382
  • Lastpage
    385
  • Abstract
    The design issues and implementation of a fault-tolerant multiprocessor system are addressed. Two design alternatives, termed failsafe and failsafe-redundant, are presented. The modular software presented previously by the authors (1989) for a tri-module redundant (TMR) system is easily transportable to the proposed architecture. The results of a reliability analysis for the two design schemes are presented. The proposed arbitration schemes can be integrated in LSI for improved reliability
  • Keywords
    computer architecture; fault tolerant computing; multiprocessing systems; redundancy; LSI; arbitration schemes; failsafe interfacing; failsafe-redundant interfacing; fault tolerant multiprocessor system; hardware architecture; reliability analysis; Circuit faults; Computer architecture; Failure analysis; Fault tolerant systems; Hardware; Microcomputers; Multiprocessing systems; Multiprocessor interconnection networks; Reliability; Signal generators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    TENCON '89. Fourth IEEE Region 10 International Conference
  • Conference_Location
    Bombay
  • Type

    conf

  • DOI
    10.1109/TENCON.1989.176963
  • Filename
    176963
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2836637