Temperature Aware Floorplanning via Geometry Programming

Power density of microprocessors is increasing with every new process generation resulting in increasingly higher chip temperatures. The high temperature of the chip greatly affects its reliability, raises the leakage power consumed to unprecedented levels, and makes cooling solutions significantly more expensive. The maximum temperature of a block in a chip depends, however, not only on its own power density, but also on the chip area in each blocks. In this paper, we employ geometric programming (GP) method for the minimum temperature and area floorplanning problem. We notice that it is a nonlinear convex problem and its optimal solution can be obtained by GP method. The numerical result shows that the difference between the original temperatures and temperatures for MCNC ami33 after optimization can be as high as 80degC degree. We have modified a floorplanning tool to include temperature as an objective for block area to reduce the hot spot temperature. We show that it is possible to find a floorplan that can reduce the maximum temperature of the chip and minimize the chip area while maintaining comparable performance.