A design methodology for the realisation of dedicated function VLSI digital filters

Outlines a design methodology for realising finite impulse response digital filters with fixed coefficients. The technique is based on the use of a primitive operator graph, which represents the filter multipliers using a minimum or near-minimum number of addition/subtraction operations. Vertex rearrangement, retiming and edge elimination techniques are then applied to form a logical graph with an efficient allocation of pipeline registers. An example of this process is given for a bit-serial realisation employing a bit-level pipeline