DocumentCode
283830
Title
A design method for cost-effective self-testing checker for optimal d-unidirectional error detecting codes
Author
Fujiwara, Eiji ; Yoshikawa, Masakatsu
Author_Institution
Fac. of Eng., Tokyo Inst. of Technol., Japan
fYear
1991
fDate
26-27 Sep 1991
Firstpage
174
Lastpage
179
Abstract
Unidirectional/asymmetric error codes have extensively been studied, not only from theoretical interest but from application to computer systems or communication systems. Recently, attention has been focused on detecting only d, not all, unidirectional errors, that is, d bits unidirectional error detecting (d-UED) codes. The paper shows a design method for a cost-effective self-testing checker for the optimal d-UED code. The checking policy is to check whether condition of the Borden code satisfies or not. The proposed checker includes the parallel weight counter, the comparator and the modulo adder in which new residue operation is defined and hence this makes the circuit self-testing. These circuits are designed to have all possible input patterns in order to satisfy self-testing property. Finally, the proposed checker has greatly reduced hardware requirements
Keywords
VLSI; built-in self test; error detection codes; integrated logic circuits; logic testing; Borden code; comparator; cost-effective self-testing checker; modulo adder; optimal d-UED code; optimal d-unidirectional error detecting codes; parallel weight counter; Application software; Built-in self-test; Circuit testing; Computer errors; Design methodology; Electrical fault detection; Error correction codes; Fault detection; Hardware; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Fault Tolerant Systems, 1991. Proceedings., Pacific Rim International Symposium on
Conference_Location
Kawasaki
Print_ISBN
0-8186-2275-X
Type
conf
DOI
10.1109/{RFTS.1991.212948
Filename
212948
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