• DocumentCode
    283831
  • Title

    A design method of SFS and SCD combinational circuits

  • Author

    Hatakenaka, Shin´ichi ; Nanya, Takashi

  • Author_Institution
    Tokyo Inst. of Technol., Japan
  • fYear
    1991
  • fDate
    26-27 Sep 1991
  • Firstpage
    168
  • Lastpage
    173
  • Abstract
    Strongly fault-secure (SFS) circuits are known to achieve the TSC goal of producing a non-codeword as the first erroneous output due to a fault. Strongly code-disjoint (SCD) circuits always map non-codeword inputs to non-codeword outputs even in the presence of faults so long as the faults are undetectable. The paper presents a new generalized design method for the SFS and SCD realization of combinational circuits. The proposed design is simple, and always gives an SFS and SCD combinational circuit which implements any given logic function. The resulting SFS/SCD circuits can be connected in cascade with each other to construct a larger SFS/SCD circuit if each interface is fully exercised
  • Keywords
    VLSI; built-in self test; error detection; fault tolerant computing; integrated logic circuits; logic testing; SCD combinational circuits; SFS; design method; logic function; strongly code disjoint circuits; strongly fault secure circuits; Circuit faults; Circuit synthesis; Combinational circuits; Design methodology; Electrical fault detection; Encoding; Fault detection; Logic circuits; Logic functions; Programmable logic arrays;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Fault Tolerant Systems, 1991. Proceedings., Pacific Rim International Symposium on
  • Conference_Location
    Kawasaki
  • Print_ISBN
    0-8186-2275-X
  • Type

    conf

  • DOI
    10.1109/{RFTS.1991.212949
  • Filename
    212949