Built-In-Self-Test Methodology for Hardwares of Dynamically Reconfigurable Computer

Aiming at the improvement of dependability of dynamically reconfigurable computers, this paper presents one methodology on Design-For-Testability (DFT) based on Built-In-Self-Test. Test subsystem for computer hardware is composed of micro-processor, co-controller, power/clock module, input/output interface module and display module. Communication module, which provides wired or wireless communication for test subsystem is included in this DFT infrastructure also. By this approach, the self-test and self-diagnosis of hardware circuits can be completed for dynamically reconfigurable computers whose design specifications comply with multiple international DFT standards. Following test tasks, such as functional test to entire board or module(s) on the board under test, interconnection test, internal and external test for a single chip, can be realized. The outline of designing verification system is given also in this paper, and experimental results support the effectiveness of this approach proposed.