Title :
A method of shuffling compactor inputs in VLSI self-testing
Author :
FURUYA, KIYOSHI ; McCluskey, Edward J.
Author_Institution :
Dept. of Electr. & Electron. Eng., Chuo Univ., Tokyo, Japan
Abstract :
Shuffling interconnections between CUT outputs and the output response compactor inputs is proposed as a scheme to decrease aliasing probability. A spot error is defined as a multiple bit error adjacent in space and in time. The condition for preventing aliasing for a predetermined size of single spot error is presented. Block based shuffling and the shortened one are proposed to realize the required distance properties. The effect of shuffling against multiple spot errors is investigated by simulation
Keywords :
VLSI; built-in self test; digital integrated circuits; probability; CUT outputs; VLSI self-testing; aliasing probability; block based shuffling; multiple bit error; multiple spot errors; output response compactor inputs; Automatic testing; Built-in self-test; Circuit faults; Circuit simulation; Circuit testing; Compaction; Integrated circuit interconnections; Linear feedback shift registers; Manufacturing; Very large scale integration;
Conference_Titel :
Fault Tolerant Systems, 1991. Proceedings., Pacific Rim International Symposium on
Conference_Location :
Kawasaki
Print_ISBN :
0-8186-2275-X
DOI :
10.1109/{RFTS.1991.212961
