DocumentCode
283847
Title
Trustworthy bus arbiter by alternate-data retry
Author
Tokito, Kazuo ; Kurokawa, Takakazu ; Koga, Yoshiaki
Author_Institution
Dept. of Comput. Sci., Nat. Defense Acad., Yokosuka, Japan
fYear
1991
fDate
26-27 Sep 1991
Firstpage
52
Lastpage
57
Abstract
A simple trustworthy bus arbiter by alternate-data retry is proposed. Trustworthiness is considered to be such a property that system responses are always trustworthy whether there exist faults or not in the system. The arbiter has two phase operations to select a parallel decision decentralized arbiter which is used in Futurebus, MultibusII and so on. The presented scheme does not permit that two or more modules are selected as bus masters to cause a fatal system operation. The arbiter presented by alternate-data retry is operated in a specially defined Id code space. Three self complementary-codes named complementary mirrored-code, reversible-ordered-code and continuous two-bit changing code are presented to be applied to the proposed arbiter
Keywords
codes; fault tolerant computing; logic circuits; logic design; system buses; Futurebus; Id code space; MultibusII; alternate-data retry; bus masters; complementary mirrored-code; continuous two-bit changing code; fatal system operation; parallel decision decentralized arbiter; phase operations; reversible-ordered-code; self complementary-codes; system responses; trustworthy bus arbiter; Circuit faults; Circuit testing; Computer science; Hardware; Logic gates; Los Angeles Council; Redundancy; Space technology; System testing; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Fault Tolerant Systems, 1991. Proceedings., Pacific Rim International Symposium on
Conference_Location
Kawasaki
Print_ISBN
0-8186-2275-X
Type
conf
DOI
10.1109/{RFTS.1991.212966
Filename
212966
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