DocumentCode
2840522
Title
Architecture and compiler enhancements for PA-RISC workstations
Author
Odnert, D. ; Hansen, R. ; Dadoo, M. ; Laventhal, M.
Author_Institution
Hewlett-Packard Co., Cupertino, CA, USA
fYear
1991
fDate
Feb. 25 1991-March 1 1991
Firstpage
214
Lastpage
218
Abstract
A set of extensions to Hewlett-Packard´s Precision RISC (reduced instruction set computer) Architecture is described. These extensions allow a higher level of floating-point performance and represent the first wave of enhancements to PA-RISC inspired by workstation requirements. The role of these architecture changes and the enhanced optimization capabilities of the PA-RISC compilers are reviewed with an emphasis on their impact on application performance. A discussion of compatibility with previous PA-RISC systems and HP´s MC680*0-based workstations is also presented.<>
Keywords
computer architecture; program compilers; reduced instruction set computing; workstations; Hewlett Packard; PA-RISC compilers; PA-RISC workstations; application performance; floating-point performance; optimization capabilities; Application software; Computer aided instruction; Computer architecture; Coprocessors; Laboratories; Optimizing compilers; Performance analysis; Reduced instruction set computing; Registers; Workstations;
fLanguage
English
Publisher
ieee
Conference_Titel
Compcon Spring '91. Digest of Papers
Conference_Location
San Francisco, CA, USA
Print_ISBN
0-8186-2134-6
Type
conf
DOI
10.1109/CMPCON.1991.128809
Filename
128809
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