Title :
A system for efficiently self-reconstructing E-1½ track switch torus arrays
Author :
Horita, Tadayoshi ; Takanami, Itsuo
Author_Institution :
Dept. of Comput. & Inf. Sci., Iwate Univ., Morioka, Japan
Abstract :
A mesh-connected processor array consists of many similar processing elements (PEs), which can be executed in both parallel and pipeline processing. For the implementation of an array of large numbers of processors, it is necessary to consider some fault tolerant issues to enhance the (fabrication-time) yield and the (run-time) reliability. We introduce the E-1½-TS torus array ray model and apply the EAR method (that is an extended approximate reconfiguration method) to the array. We show that the E-1½-TS torus arrays with the hardware realization of the EAR algorithm are very efficient at the point of the array yield (or reliability) and suitable for run-time as well as fabrication-time fault-tolerance for mesh or torus connected processor arrays even though an additional logic circuit (about 200 gates per processor) is required
Keywords :
fault tolerant computing; parallel architectures; pipeline processing; reconfigurable architectures; E-1½ track switch torus array self-reconstruction; EAR method; fabrication-time yield; fault tolerance; logic circuit; mesh-connected processor array; parallel processing; pipeline processing; processing elements; run-time reliability; Circuit faults; Concurrent computing; Ear; Educational institutions; Fault tolerance; Hardware; Logic arrays; Pipeline processing; Runtime; Switches;
Conference_Titel :
Parallel Architectures, Algorithms and Networks, 2000. I-SPAN 2000. Proceedings. International Symposium on
Conference_Location :
Dallas, TX
Print_ISBN :
0-7695-0936-3
DOI :
10.1109/ISPAN.2000.900260