FPGA implementation of an OFDM-WLAN synchronizer

In this paper, we present a timing and frequency synchronization scheme and its FPGA implementation for IEEE 802.11a WLAN systems. In the scheme, an efficient double auto-correlation method based on short training symbols is used for timing synchronization. The performance of the proposed method is comparable or even superior to that of the conventional timing synchronization method under multipath fading channels. By averaging the correlation over four short training symbols, the accuracy of frequency synchronization using short training symbols can be improved to a level that the fine frequency synchronization process using long training symbols in the conventional scheme would not be needed. Thus both timing and frequency synchronization can be achieved using short training symbols alone to reduce computational complexity and overhead. Furthermore, the hardware architecture of the proposed synchronization scheme is developed. The synchronizer is mainly made up of correlator, angle calculator and peak detector, which are implemented by an iterative process, a CORDIC circuit and a finite state machine, respectively. Such an architecture results in low implementation complexity and low computational latency.