Noise analysis of a reduced complexity pipeline analog-to-digital converter

This paper presents a mathematical analysis of the noise generated within a 12-bit reduced complexity pipeline analog-to-digital converter (ADC) to demonstrate the effect of noise on the device performance. A modified flash ADC was employed instead of the traditional full flash ADC to implement the sub-ADC in the proposed pipeline ADC to reduce the device complexity and attain lower system power consumption. The 12-bit pipeline ADC is operated at 400 MHz and generates total noise power of 3.38/spl times/10/sup -12//spl middot//spl Delta/f (V/sup 2/) at this frequency. The developed model provides a good estimation of the noise generated by the circuit and gives an accurate prediction on the circuit noise performance. Also, such model provides good guide for further improvement of the circuit performance.