Design of video compression system based on DSP_FPGA

Author

Hui, Zhao ; Hongxing, Sun

Author_Institution

Sch. of Electron. & Inf. Eng., Univ. of Sci. & Technol., Anshan, China

fYear

2009

fDate

17-19 June 2009

Firstpage

5432

Lastpage

5437

Abstract

The video compression system is designed based on high speed Digital Signal Processing (DSP) and Field Programmable Gate Array(FPGA), and the implementation of JPEG2000 image compression algorithm is discussed. Hardware constitutes and working principle of the digital image compression system are introduced, and FPGA control logic, DSP peripheral circuit designing and the basic technology of image compression and structure of wavelet algorithm are modified are specifically discussed in detail. The system is favorable for its integrated functions, simple structures and flexible complier, and the high speed transmission and the mass data real-time compression are realized.

Keywords

data compression; digital signal processing chips; field programmable gate arrays; video coding; wavelet transforms; DSP peripheral circuit; FPGA; JPEG2000 image compression algorithm; digital image compression system; field programmable gate array; flexible complier; high speed digital signal processing; video compression system; wavelet algorithm; Algorithm design and analysis; Digital signal processing; Field programmable gate arrays; Hardware; Image coding; Programmable logic arrays; Signal design; Signal processing algorithms; Transform coding; Video compression; DSP; FPGA; JPEG2000; image compression;

fLanguage

English

Publisher

ieee

Conference_Titel

Control and Decision Conference, 2009. CCDC '09. Chinese

Conference_Location

Guilin

Print_ISBN

978-1-4244-2722-2

Electronic_ISBN

978-1-4244-2723-9

Type

conf

DOI

10.1109/CCDC.2009.5195161

Filename

5195161