A Novel Low Power Noise Tolerant High Performance Dynamic Feed through Logic Design Technique

In this paper a new design technique is proposed using FTL (Feed through Logic) concept for high performance dynamic CMOS logic with high noise immunity and low power. FTL improves the performance of arithmetic circuits with a very long logic depth. In spite of its performance advantage, FTL suffers from reduced noise margin, direct path current and non-zero nominal low output voltage. The proposed technique removes the charge sharing problem and increases the noise immunity of high performance dynamic FTL circuit. In order to evaluate the efficacy of the proposed technique a high performance dynamic 2-input AND gate is designed and realized using the proposed technique. A comparative analysis of the proposed technique, Feed Through Logic and Domino Logic has been done in terms of noise immunity, power dissipation and delay. A comparative analysis is also carried out by simulating the above dynamic logic circuits in 180nm and 90nm technology with supply voltages of 1.8V and 1V respectively. At 180nm technology the Average Noise Threshold Energy (ANTE) & Energy normalized ANTE of proposed technique is improved by 4.35X & 1.65X over conventional Domino and 1.96X & 3.49X over conventional FTL. Power dissipation is reduced by 3.69X & 3.50X over conventional Domino and conventional FTL respectively.