• DocumentCode
    2848290
  • Title

    A 40-NS, 144-bit N-channel MOS-IC memory

  • Author

    Yamamoto, Hiroshi ; Shiraishi, Masashi ; Kurosawa, T.

  • Author_Institution
    Nippon Electric Co., Ltd., Tokyo, Japan
  • Volume
    XII
  • fYear
    1969
  • fDate
    19-21 Feb. 1969
  • Firstpage
    40
  • Lastpage
    41
  • Abstract
    A monolithic MOS 144-bit random access memory has been fabricated, using N-channel MOS transistors. The memory operates with a 10-ns access time, 30-ns non-destructive read cycle time, and a 40-ns write cycle time.
  • Keywords
    Assembly; Capacitance; Circuits; Large scale integration; MOSFETs; Packaging; Read-write memory; Substrates; Variable structure systems; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference. Digest of Technical Papers. 1969 IEEE Internationa
  • Conference_Location
    Philadelphia, PA, USA
  • Type

    conf

  • DOI
    10.1109/ISSCC.1969.1154744
  • Filename
    1154744
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2848290