DocumentCode
2848663
Title
Projection of delay in Ge and Si high-speed switching circuits
Author
Hachtel, G.
Author_Institution
IBM Corp., Yorktown Heights, N.Y., USA
Volume
XII
fYear
1969
fDate
19-21 Feb. 1969
Firstpage
174
Lastpage
175
Abstract
This paper will describe a 1-dimensional transistor analysis program featuring Fermi statistics, saturated velocity and transient effects that predicts switching delays (loaded, packaged CSEF circuits) Of 50 ps(Ge) and 150 ps(SI) for near-ultimate impurity profiles, and at current densities of 105A/cm2.
Keywords
Capacitance; Circuit simulation; Current density; Delay; Electron mobility; Impurities; Statistics; Switches; Switching circuits; Transient analysis;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1969 IEEE Internationa
Conference_Location
Philadelphia, PA, USA
Type
conf
DOI
10.1109/ISSCC.1969.1154769
Filename
1154769
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