Parallel algorithms and systolic array designs for RSA cryptosystem

Author

Zhang, Chang N. ; Martin, Herold L. ; Yun, David Y Y

Author_Institution

Dept. of Electr. Eng., North Carolina A&T State Univ., Greensboro, NC, USA

fYear

1988

fDate

25-27 May 1988

Firstpage

341

Lastpage

350

Abstract

Two algorithms for computing very large integer modular exponentiation are proposed. One is based on a recording technique that significantly reduces the total number of modular multiplications. The second is parallel algorithm that can be implemented by two parallel processors and achieves optimal performance. Two corresponding systolic array designs are developed. The main advantage of these systolic architectures is to provide a potentially higher throughput for a large number of computations, namely, encryptions and decryptions in an RSA cryptosystem.<>

Keywords

cellular arrays; cryptography; digital arithmetic; parallel algorithms; RSA cryptosystem; decryptions; encryptions; modular multiplications; parallel algorithm; parallel processors; recording technique; systolic architectures; systolic array designs; very large integer modular exponentiation; Algorithm design and analysis; Computer architecture; Computer science; Cryptography; Design engineering; Equations; Parallel algorithms; Public key; Systolic arrays; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Systolic Arrays, 1988., Proceedings of the International Conference on

Conference_Location

San Diego, CA, USA

Print_ISBN

0-8186-8860-2

Type

conf

DOI

10.1109/ARRAYS.1988.18074

Filename

18074