• DocumentCode
    2849656
  • Title

    Design considerations for a high-speed bipolar read-only memory

  • Author

    Bergh, A. ; Barrett, John ; Price, Jack

  • Author_Institution
    Hewlett-Packard Laboratories, Palo Alto, CA, USA
  • Volume
    XIII
  • fYear
    1970
  • fDate
    18-20 Feb. 1970
  • Firstpage
    66
  • Lastpage
    67
  • Abstract
    A monolithic, fully-decoded 1024-bit read-only memory, with less than 50-ns access time and 350-mW power dissipation, will be discussed. The ROM can be bit-organized with a coincident select structure to minimize pin count and address decoders.
  • Keywords
    Circuit synthesis; Decoding; Electronics packaging; Integrated circuit packaging; Inverters; Laboratories; Logic design; Power dissipation; Propagation delay; Read only memory;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference. Digest of Technical Papers. 1970 IEEE International
  • Conference_Location
    Philadelphia, PA, USA
  • Type

    conf

  • DOI
    10.1109/ISSCC.1970.1154838
  • Filename
    1154838
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2849656