Title :
A probabilistic model for clock skew
Author :
Kugelmass, Steven D. ; Steiglitz, Kenneth
Author_Institution :
Dept. of Comput. Sci., Princeton Univ., NJ, USA
Abstract :
A probabilistic model for the accumulation of clock skew in synchronous systems is presented. The model is used to derive upper bounds for expected skew and its variance, in tree distribution systems with N synchronously clocked processing elements. The results are applied to two specific models for clock distribution. In the first, which is called metric-free, the skew in a buffer stage is Gaussian with a variance independent of wire length. The second, metric, model, is intended to reflect VLSI constraints: the clock skew in a stage is Gaussian with a variance proportional to wire length, and the distribution tree is an H-tree embedded in the plane. Upper bounds on skew are obtained for both models. Estimates of the constants of proportionality as well as the asymptotic behavior have been obtained and verified by simulation.<>
Keywords :
VLSI; clocks; delays; synchronisation; VLSI constraints; clock distribution tree; clock skew; global signal distribution; metric free tree; metric tree; probabilistic model; processor arrays; skew accumulation; synchronous systems; tree distribution systems; wire length; Clocks; Computer science; Equations; Predictive models; Solid modeling; Timing; Topology; Upper bound; Very large scale integration; Wire;
Conference_Titel :
Systolic Arrays, 1988., Proceedings of the International Conference on
Conference_Location :
San Diego, CA, USA
Print_ISBN :
0-8186-8860-2
DOI :
10.1109/ARRAYS.1988.18091
