A new self-organisation strategy for floorplan design

Floorplanning of VLSI circuits is a complex combinatorial problem. A floorplanning approach based on space mapping is presented. The mapping is considered as a weighted projection between two spaces, input circuit description space and output floorplan space, with the projection between the two being carried out by a self-organizing process based on Kohonen´s self-organizing networks. The technique was implemented and tested on difficult benchmarks floorplanning problem producing good results. Optimization and floorplan solution production is achieved by the means of weighted projection with the weights computed in a self-organizing manner