Adopting the Scan Approach for a Fault Tolerant Asynchronous Clock Generation Circuit

We describe the test concept for a clock generation unit that implements one instance of a distributed agreement algorithm, in hardware. The challenge of testing this unit lies in its asynchronous nature. We propose a suitable partitioning of the self-timed circuit and the introduction of two scan chains whose operation is carefully interlocked. In this way we can achieve a coverage of 100% for single stuck-at faults with very low overheads in term of speed penalty and test pins.