A single 1.5-V digital chip for a 106-synapse neural network

A single-chip architecture for a 10⁶-synapse neural network is proposed. It operates on a 1.5-V dry cell so that it can be used in portable equipment. An on-chip DRAM cell array stores 10⁶ 8-b synapse weights digitally. These are readily programmable and refreshable. A pitch-matched interconnection and a combinational unit circuit used for summing product provide a tight layout by eliminating bus lines between the memory cell array and the product-summation circuit. A dynamic data transfer circuit directly coupled to the DRAM cell array, together with 1.5-V operation of the entire chip, reduces the power dissipation to 75 mW. The 256 parallel circuits for summing product provide a processing speed of 1.37 gigaconnections/s. The memory and the processing circuits can be integrated on a 15.4-mm×18.6-mm chip by using a 0.5-μm CMOS design rule