A multiprocessor system utilizing enhanced DSPs for image processing

Author

Ueda, Hirotada ; Kato, Kanji ; Matsushima, Hirokazu ; Kaneko, Kenji ; Ejiri, Masakazu

Author_Institution

Hitachi Ltd., Tokyo, Japan

fYear

1988

fDate

25-27 May 1988

Firstpage

611

Lastpage

620

Abstract

A general-purpose image processor (GPIP) consisting of 64 digital signal processors (DSPs) in a 0.31-m/sup 3/ box is proposed to perform a wide range of image processing tasks. A high-speed DSP called DSP-i has been especially developed for this purpose. It has a highly parallel architecture with a two-level instruction hierarchy, multibank cache, and multiprocessor interface. The DSP-i machine cycle is 50 ns. A novel ring shift register bus architecture offers a flexible structure and an efficient data-exchange method for the system. Along with four proposed operation modes, it cuts the multiprocessing overhead to as little as 20%. The performance of the GPIP is 1000 MOPS (million operations per second).<>

Keywords

computerised picture processing; parallel architectures; parallel machines; 1000 MOPS; 16 bit; DSP-i; data-exchange; digital signal processors; general-purpose image processor; million operations per second; multibank cache; multiprocessing overhead; multiprocessor interface; multiprocessor system; ring shift register bus architecture; two-level instruction hierarchy; CMOS technology; Digital signal processing; Digital signal processors; Flexible structures; Image processing; Laboratories; Multiprocessing systems; Parallel architectures; Shift registers; Signal processing;

fLanguage

English

Publisher

ieee

Conference_Titel

Systolic Arrays, 1988., Proceedings of the International Conference on

Conference_Location

San Diego, CA, USA

Print_ISBN

0-8186-8860-2

Type

conf

DOI

10.1109/ARRAYS.1988.18098

Filename

18098