Performance Analysis of Networks-on-Chip Routers

Routers are pivotal modules in networks-on-chip (NoC)-based designs. Therefore, acquiring an accurate estimation of the router performance is an essential parameter at early design phases. In this paper, we explain how queuing analysis could be applied to a NoC-based system to extract desired performance parameters. We focus on the analysis of routers since they are at the heart of any NoC-based system. Because there are several possible NoC architectures, we first show the NoC internal structure and how router design depends on the type of network topology. Next, we discuss different types of router structures that could be used. We used Markov chain analysis to derive an analytical model for an input-queue mesh-based router as a case study. Detailed analysis were carried out on the model simulation results to show its response to the change in different design parameters.