• DocumentCode
    2851817
  • Title

    Computer-generated IGFET layout using a vertically-packed weinberger arrangement

  • Author

    Schweikert, D.

  • Author_Institution
    Bell Telephone Labs., Inc., Murray Hill, NJ, USA
  • Volume
    XIV
  • fYear
    1971
  • fDate
    17-19 Feb. 1971
  • Firstpage
    118
  • Lastpage
    119
  • Abstract
    A program which vertically packs IGFET logic circuit nodes in the modular Weinberger arrangement will be discussed. Program output can interface directly with artwork generators. Area savings of up to 50% have been obtained.
  • Keywords
    Computer errors; Counting circuits; Delay; Fabrication; Laboratories; Large scale integration; Layout; Logic circuits; Telephony; Wire;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference. Digest of Technical Papers. 1971 IEEE International
  • Conference_Location
    Philadelphia, PA, USA
  • Type

    conf

  • DOI
    10.1109/ISSCC.1971.1154959
  • Filename
    1154959
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2851817