Title :
Pattern matching and parallel processing with CCD technology
Author :
PedroN, Volnei A. ; Agranat, Ahmn ; Neugebauer, Charles ; Yariv, Amnon
Author_Institution :
California Inst. of Technol., Pasadena, CA, USA
Abstract :
A fully parallel charge coupled device (CCD) memory chip of N address lines is presented. It detects, in just one clock cycle, a perfect matching between input pattern and any of the stored patterns. It detects in fewer than N cycles the best matching in case a perfect one does not exist. The charge packets, representing binary words, are generated by external pulses that are applied to the chip through data input lines and then are compared to the data applied to the address lines. The chip architecture is described. This chip is suitable for applications in pattern recognition, Kanerva memories, data decoders, and other systems that require peak detection or Hamming distance calculation. Typical results expected in these kinds of implementations based on similar devices are reported
Keywords :
charge-coupled device circuits; integrated memory circuits; parallel processing; pattern recognition; CCD technology; Hamming distance calculation; Kanerva memories; address lines; chip architecture; data decoders; fully parallel CCD memory chip; input pattern; parallel processing; pattern matching; pattern recognition; perfect matching; Charge coupled devices; Charge-coupled image sensors; Clocks; Decoding; Hamming distance; Impedance matching; Parallel processing; Pattern matching; Pattern recognition; Pulse generation;
Conference_Titel :
Neural Networks, 1992. IJCNN., International Joint Conference on
Conference_Location :
Baltimore, MD
Print_ISBN :
0-7803-0559-0
DOI :
10.1109/IJCNN.1992.227105
