• DocumentCode
    2852623
  • Title

    Block and track method for automated layout generation of MOS-LSI arrays

  • Author

    Kozawa, T. ; Horino, H. ; Watanabe, K. ; Nagata, M. ; Hukuda, H.

  • Author_Institution
    Hitachi, Ltd., Tokyo, Japan
  • Volume
    XV
  • fYear
    1972
  • fDate
    16-18 Feb. 1972
  • Firstpage
    62
  • Lastpage
    63
  • Abstract
    An automated layout program with a block and track concept will be described. The program, which takes logic descriptions, can generate composite-patterns for single-chip calculator MOS-LSI arrays within 600 seconds computing time with manual-comparable chip areas.
  • Keywords
    Automatic logic units; Calculators; Equations; Humans; Integrated circuit interconnections; Large scale integration; Logic arrays; Logic circuits; Logic design; Wiring;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference. Digest of Technical Papers. 1972 IEEE International
  • Conference_Location
    Philadelphia, PA, USA
  • Type

    conf

  • DOI
    10.1109/ISSCC.1972.1155010
  • Filename
    1155010
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2852623