A unified on-line and off-line BIST scheme for ROMs

Author

Yeung, Daniel ; Sun, Xiaoling ; Olson, Michael

Author_Institution

Dept. of Electr. Eng., Alberta Univ., Edmonton, Alta., Canada

fYear

1995

fDate

17-19 May 1995

Firstpage

469

Lastpage

472

Abstract

A novel built-in self-test (BIST) scheme is proposed for read-only memories (ROMs). This scheme, based on memory partitioning and signature analysis, supports both on-line and off-line testability. With a hardware cost comparable to parity checking, the on-line testing scheme provides much better error detection capability than conventional strategies. The off-line test retains a high error coverage of at least 99.9985%. In addition, the hardware resources are unified; thus, the total hardware cost is greatly reduced in comparison to incorporating the two test strategies separately

Keywords

VLSI; built-in self test; error detection; integrated circuit testing; logic testing; parallel architectures; read-only storage; ROMs; built-in self-test; error coverage; error detection capability; hardware cost; hardware resources; memory partitioning; off-line BIST scheme; on-line BIST scheme; read-only memories; signature analysis; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Compaction; Costs; Error correction; Hardware; Read only memory; Registers;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications, Computers, and Signal Processing, 1995. Proceedings., IEEE Pacific Rim Conference on

Conference_Location

Victoria, BC

Print_ISBN

0-7803-2553-2

Type

conf

DOI

10.1109/PACRIM.1995.519571

Filename

519571