Advancements in at-speed array BIST: multiple improvements

This paper discusses the unique challenges in constructing an architecture and methodology for testing a 1 GHz 65 nm Embedded DRAM in an ASIC environment. The concepts of multiplication of both test commands and test clock frequency are discussed in detail. The novel technique of command multiplication is thoroughly explored. The inherent benefits of this design point is examined as it relates to test circuit design, BIST sharing, and chip level wiring in comparison to traditional scan or parallel based array BIST architectures. Attention is also paid to various methods used for supporting at-speed/high-speed test clock generation from a low speed tester and the important influence this has on test cost and test quality.