DocumentCode
2852658
Title
Combining partitioning and global routing in sea-of-cells design
Author
Korte, B. ; Promel, H.J. ; Steger, A.
Author_Institution
Forschungsinst. Fuer Diskrete Math., Bonn, West Germany
fYear
1989
fDate
5-9 Nov. 1989
Firstpage
98
Lastpage
101
Abstract
A report is presented on the partitioning algorithm of a novel automatic layout system for the sea-of-cells design. The algorithm is based on graph partitioning. The principal novelty of the approach is that a global routing is obtained after each iteration to precisely estimate the number of nets crossing a cut. The author also report on the successful application to CMOS chips of the IBM ES/370 chip set.<>
Keywords
CMOS integrated circuits; circuit layout CAD; logic CAD; logic arrays; CMOS chips; IBM ES/370 chip set; automatic layout system; cut crossing; estimate; global routing; graph partitioning; iteration; nets; partitioning algorithm; sea-of-cells design; Algorithm design and analysis; CMOS technology; Clustering algorithms; Contracts; Laboratories; Libraries; Partitioning algorithms; Power systems; Routing; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer-Aided Design, 1989. ICCAD-89. Digest of Technical Papers., 1989 IEEE International Conference on
Conference_Location
Santa Clara, CA, USA
Print_ISBN
0-8186-1986-4
Type
conf
DOI
10.1109/ICCAD.1989.76913
Filename
76913
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